View LV52207NXB-VH_8835593.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? semiconductor components industries, llc, 2015 1 publication order number: november 2015- rev. 1 lv52207nxb/d lv52207nxb led boost driver, dual channel, pwm, 1-wire dimming overview the lv52207nxb is a high voltage boost driver for led drive with 2 channels adjustable constant current sources. features ? operating voltage from 2.7v to 5.5v ? integrated 40v mosfet ? 1-wire 255 level digital and pwm dimming ? supports cabc ? 600khz switching frequency ? 37.5v overvoltage protection (ovp) threshold typical applications led display backlight control fig1. 5x2 led application www.onsemi.com pin connection ordering information ordering code: LV52207NXB-VH package wlp9j (1.31x1.31) (pb-free / halogen free) shipping (qty / packing) 5000 / tape & reel ? for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. http://www.onsemi.com/pub_link/collateral/brd8011-d.pdf wlp9j, 1.31x1.31, 0.4mm pitch (1.31mm x 1.31mm, amax=0.65 mm) top view rt ledo 1 ledo 2 pwm fcap gnd en vin sw a b c 123
lv52207nxb www.onsemi.com 2 specifications absolute maximum ratings at ta = 25 ? c (note 1) parameter symbol conditions ratings unit maximum supply voltage v cc max v cc 6 v maximum pin voltage1 v1 max sw 40 v maximum pin voltage2 v2 max other pin 5.5 v allowable power dissipation pd max ta=25 ? c (note 2) 1.05 w operating temperature topr ? 40 to +85 ? c storage temperature tstg ? 55 to +125 ? c 1. stresses exceeding those listed in the maximum rating table may damage the device. if any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 2. mounted on the following board: 70mm70mm1.6mm (4 layer glass epoxy) 3. absolute maximum ratings represent the values which cannot be exceeded for any length of time. 4. when the device is used within the range of absolute maximum ratings, as a result of continuous usage under high temperature, h igh current, high voltage, or drastic temperature change, the reliab ility of the ic may be decrease. please contact on semiconduct or for the further details. recommended operating conditions at ta = 25 ? c (note 5) parameter symbol conditions ratings unit supply voltage range1 v cc op vcc 2.7 to 5.5 v pwm frequency f pwm pwm pin input signal 300 to 100k hz min. duty% on pwm pin d min pwm pwm pin input signal 0.9% 5. functional operation above the stresses listed in the recommended o perating ranges is not implied. extended exposure to stresse s beyond the recommended operating ranges limits may affect device reliability. electrical characteristics analog block (note 6) at ta=25c, vcc=3.6v, rt resistor=63.4k ? unless otherwise specified parameter symbol conditions ratings unit min typ max standby current dissipation icc1 en=pwm=l 0 2.0 ? a dc/dc current dissipation1 icc2 device enable, switching 0.6 mhz and no load 0.7 1.2 ma feedback voltage v fb ledo1, 2=20ma 0.2 v output current1 i o1 ledo1, ledo2, lediset=20ma duty=100% 19.6 20 20.4 ma output current matching1 i om1 ledo1, ledo2, lediset=20ma duty=100% (imax ? iavg) / iavg 0.3 2.0 % ledo1, 2 max current i max ledo1 ledo2 40 ma ledo1, 2 leak current i leak ledo1 ledo2 1.0 ? a ovp voltage v ovp sw_pin over voltage threshold 36 37.5 39 v ledo_ovp voltage v ovp,led ledo_pin over voltage threshold ledo_dc rising 4.2 4.5 5.0 v sw out on resistance r on i l =100ma 300 m ? nmos switch current limit i lim 1.0 1.5 a osc frequency f osc 500 600 750 khz high level input voltage v inh en pwm 1.2 v cc v low level input voltage v inl en pwm 0 0.4 v under voltage lockout v uvlo vin falling 2.2 v en pin output voltage for acknowledge v ack r pull-up =15k ? 0.4 v 6. product parametric performance is indicated in the electrical characteristics for t he listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions.
lv52207nxb www.onsemi.com 3 recommended en pwm timing at ta=25c, v cc =3.6v, unless otherwise specified parameter symbol conditions ratings unit min typ max dimming mode selectable time t sel 1.0 2.2 ms delay time to start digital mode detection t w0 100 ? s low time to switch to digital mode t w1 260 ? s en pin low time to shutdown t off, en 2.5 ms pwm pin low time to shutdown t off, pwm 20 ms 1-wire start time for digital mode programming t start 2.0 ? s 1-wire end time for digital mode programming t end 2.0 360 ? s 1-wire high time of bit 0 t h0 bit detection=0 2.0 180 ? s 1-wire low time of bit 0 t l0 bit detection=0 th0 ? 2 360 ? s 1-wire high time of bit 1 t h1 bit detection=1 tl1 ? 2 360 ? s 1-wire low time of bit1 t l1 bit detection=1 2.0 180 ? s dcdc startup delay t del 5 ms delay time of acknowledge t ackd 2 ? s duration of acknowledge t ack 512 ? s
lv52207nxb www.onsemi.com 4 package dimensions unit : mm wlcsp9, 1.31x1.31 case 567hx issue c seating plane 0.05 c notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. coplanarity applies to the spherical crowns of the solder balls. 4. backside coating is optional. 2x dim a min max ??? millimeters a1 d 1.31 bsc e b 0.21 0.31 e 0.40 bsc 0.65 e d a b pin a1 reference a 0.05 b c 0.03 c 0.08 c 9x b 12 3 c b a 0.10 c a a1 c 0.16 0.26 1.31 bsc 0.40 0.20 9x dimensions: millimeters soldering footprint* 0.05 c 2x top view side view bottom view note 3 e recommended a1 package outline e pitch 0.40 pitch detail a note 4 backside detail a a3 a3 0.025 ref coating
lv52207nxb www.onsemi.com 5 block diagram l1 : vls3012e-4r7m (tdk), vlf504015-4r7 (tdk) vls3012e-100m (tdk), vlf504015-100m (tdk) d1 : mbr0540t1 (on semiconductor), nsr05f40 (on semiconductor) c2 : grm21br71h105k (murata), c1608x5r1h105k (tdk) fig2. block diagram pin connection top view rt ledo 1 ledo 2 pwm fcap gnd en vin sw a b c 123
lv52207nxb www.onsemi.com 6 pin function pin # pin name description a1 rt connecting a resistor termina l for full scale led current setting a2 ledo2 constant current output_pin2 a3 ledo1 constant current output_pin1 b1 pwm pwm dimming input (active high). b2 fcap filtering capacitor terminal for pwm mode b3 gnd ground c1 en 1-wire control and enable control input (active high). c2 vin supply voltage. c3 sw switch pin. drain of the internal power fet. pd-max mounted on the following board : 70 mm ? 70 mm ? 1.6 mm (4 layer glass epoxy)
lv52207nxb www.onsemi.com 7 led current setting (max sink current) led_full current is set by an external resistor connected between the rt pin and ground. _ 2113 ? : rt pin dc voltage; typically 0.6 v : rt pin resistor to ground eg: rt_res= 63.4 k ? at typical v rt _ 2113 ? 2113 ? . . 19.99 ? 20 brightness control the lv52207nxb controls the dc current of the dual channels. the dc current control is normally referred to as analog dimming mode. the lv52207nxb can receive digital commands at the en pin (1-wire dig ital interface, known as digital mode ) and the pwm signals at the pwm pin (pwm interface, known as pwm mode ) for brightness dimming. dimming mode selection dimming mode is selected by a specific pattern of the en pin within t sel of 1.0 ms from the startup of the device every time. digital mode to enter digital mode, en pin should be taken high for more than t w0 =100 ? s from the first rising edge and keep low state for t w1 = 260 ? s before t sel =1ms. when using digital mode, the pwm pin should be kept high. it is required sending the device address byte and the data byte to select ledi. the bit detection is determined by the ratio of t h and t l (see fig5). the start condition for the bit transmission required en pin high for at least tstart. the end condition is required en pin low for at least tend. when data is not being transferred, en pin is set in the ?h? state. these registers are initialized with shutdown. start up and shutdown the device becomes enabled when en pin is initially taken high. the dimming mode is determined within t sel and the boost converter start up after t del . to place the device into shutdown mode, the swire must be held low for t off . for specific timings please refer to the recommended en pwmin timing table on page 3 or the below figures. digital mode fig3. start up and shutdown diagram (digital mode)
lv52207nxb www.onsemi.com 8 tl0 th0 tl1 th1 low state(bit=0) tl0 > th0 * 2 th1 > tl1 * 2 high state(bit=1) 1-wire programming figure 15 and table 2 give an overview of the protocol used by lv52207nxb. a command consists of 24 bits, including an 8-bit device address byte and a 16-bit data byte. all of the 24 bits should be transmitted together each time, and the lsb bit should be transmitted first. in the lv52207nxb, the device address (da7(msb)to da0(lsb)) is specified as ?10001111?. akct is setting for the acknowledge response. if the device address and the data byte are transferred on akct=1, the ack signal is sent from the receive si de to the send side. the acknowledge signal is issued when en pin on the send side is released and en pin on the receive side is set to low state. fig4. example of writing data fig5. bit detection diagram
lv52207nxb www.onsemi.com 9 table1. bit description led current setting rt resistor= 63.4k ? ( for i led full = 20 ma) note: if you change the rt resistor , the led currents will all change. _ ? # ; where i led_full is the current calculated above code d8 d7 d6 d5 d4 d3 d2 d1 led current(ma) 0 0 0 0 0 0 0 0 0 0 unavailable 1 0 0 0 0 0 0 0 1 0.22 2 0 0 0 0 0 0 1 0 0.30 3 0 0 0 0 0 0 1 1 0.38 4 0 0 0 0 0 1 0 0 0.47 5 0 0 0 0 0 1 0 1 0.55 6 0 0 0 0 0 1 1 0 0.63 7 0 0 0 0 0 1 1 1 0.70 8 0 0 0 0 1 0 0 0 0.78 9 0 0 0 0 1 0 0 1 0.86 10 0 0 0 0 1 0 1 0 0.94 . . . . . . 246 1 1 1 1 0 1 1 0 19.30 247 1 1 1 1 0 1 1 1 19.38 248 1 1 1 1 1 0 0 0 19.46 249 1 1 1 1 1 0 0 1 19.54 250 1 1 1 1 1 0 1 0 19.61 251 1 1 1 1 1 0 1 1 19.69 252 1 1 1 1 1 1 0 0 19.77 253 1 1 1 1 1 1 0 1 19.84 254 1 1 1 1 1 1 1 0 19.93 255 1 1 1 1 1 1 1 1 20 *default table2. data register vs led current sink bite register bit description device address (0x8f) da7 23(msb) 1 da6 22 0 da5 21 0 da4 20 0 da3 19 1 da2 18 1 da1 17 1 da0 16 1 data d15 15 data bit 15 no in formation. write 0 to this bit. d14 14 data bit 14 no in formation. write 0 to this bit. d13 13 data bit 13 no in formation. write 0 to this bit. d12 12 data bit 12 no in formation. write 0 to this bit. d11 11 data bit 11 no in formation. write 0 to this bit. akct(d10) 10 0 = acknowledge disabled 1 = acknowledge enabled d9 9 data bit 9 d8 8 data bit 8 d7 7 data bit 7 d6 6 data bit 6 d5 5 data bit 5 d4 4 data bit 4 d3 3 data bit 3 d2 2 data bit 2 d1 1 data bit 1 lsb of brightness code d0 0(lsb) data bit 0 no information.
lv52207nxb www.onsemi.com 10 pwm mode the dimming mode is set to pwm mode when it is not recognized as a digital mode within t sel . the lv52207nxb can receive the pwm signals at the pwm pin (pwm interface, also known as pwm mode ) for brightness dimming. when using pwm interface, the en pin should be kept high. if en pin is high, pwm pin alone is used to enable and disable the ic. when en pin is high and pwm pin is high , this ic is enabled. when en pin is low for more than 2.5 ms or when pwm pin is low for more than 20 ms, the ic is disabled. fig6. start up and shutdown diagram (pwm mode) ledo1 or ledo2 unused if only one channel is used, a user can turn off a branch current by connecting the unused channel to ground. if both ledo1 pin and ledo2 pin are connected to ground, boost converter will not start up. over voltage protection ( sw ovp) sw pin over-voltage protection is set at 37.5 v. this ic monitors the voltage at sw pin . when the voltage exceeds ovp threshold the switching converter stops switching. if sw terminal voltage exceeds a threshold v ovp = 37.5 v typ. for 8 cycles, boost converter enters shutdown mode. in order to restart the ic, swire signal must be used again. over voltage protection ( ledo ovp) led pin over-voltage protection is set at 4.5 v (rising) and 3.5 v (falling). this ic monitors the voltage at ledo1 pin and ledo2 pin . when the voltage exceeds ledo ovp threshold the switching converter stops switching. led current sink keep. open led protection when one led string becomes open: if one led string is open, open channel voltage is approximately ground, the boost output voltage is increased and other ledo channel voltage is increased. when sw pin vo ltage is reached the sw ovp threshold the lv52207nxb?s switching converter stops switching. when the other ledo pin voltage reaches the ledo ovp threshold the lv52207nxb?s switching converter stops switching. when both led strings become open: if both led strings are open, ledo1 pin voltage and ledo2 pin voltage are approximately ground and the boost output voltage is increased when sw pin voltage is reached the sw ovp threshold the lv52207nxb?s switching converter stops switching. over current protection current limit value for built-in power mos is around 1.5 a. the power mos is turned off for each switching cycle when peak drain current exceeds the limit value. under voltage lock out (uvlo) uvlo operation works when vin terminal voltage is below 2.2 v. thermal shutdown when chip temperature is too high, boost converter is stopped.
lv52207nxb www.onsemi.com 11 application circuit diagram pwm dimming mode en pin can be used to enable or disable pwm dimming mode pwm pin can be used to enable or disable 1-wire dimming mode pwm pin can be used to enable or disable
lv52207nxb www.onsemi.com 12 1-wire dimming mode en pin can be used to enable or disable 1-wire dimming mode and pwm dimming mode (cabc) note : start-up sequence during tw0 period of 1-wire, it is necessary to hold pwm "high". fig7. various application circuit diagrams
lv52207nxb www.onsemi.com 13 typical characteristics (vin=3.6 v, l=10 ? h, t=25 ? c, unless otherwise specified) efficiency vs pwm dimming (20 ma/string) note: ?4s2p? means 2 strings of 4 series leds per string. pwm dimming 1-wire dimming cabc dimming
lv52207nxb www.onsemi.com 14 start up waveform shutdown waveform switching waveform
lv52207nxb www.onsemi.com 15 packing specification of embossed carrier taping wlp9/9j (1.311.31) mm / (1.39 1.21) mm
lv52207nxb www.onsemi.com 16
lv52207nxb www.onsemi.com 17
lv52207nxb www.onsemi.com 18 on semiconductor and the on logo are registered trademarks of semiconductor components industries, llc (scillc) or its subsidiaries in the united st ates and/or other countries. scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a lis ting of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent-marking.pdf . scillc reserves the right to make changes with out further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any parti cular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specific ations can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated fo r each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc pro ducts are not designed, intended, or authorized for use as com ponents in systems int ended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees ar ising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that sci llc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject t oall applicable copyright laws and is not for resale in any manner.

▲Up To Search▲

Price & Availability of LV52207NXB-VH

	To Download LV52207NXB-VH Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .